1. Field of the Invention
The present invention relates, in general, to testing of integrated circuits, and, more specifically, to an improved test access circuit and method of controlling test access circuits to facilitate access to embedded test controllers in circuit modules associated with test access circuits.
2. Description of Related Art
As complexity of integrated circuits continues to increase, partitioning of the integrated circuits into blocks or modules becomes necessary to simplify the design, verification, physical implementation, test and enable concurrent engineering of the blocks. It is anticipated that block reuse from one chip to the next or from one design team to another (possibly from different companies) will become the standard in a near future.
The problem addressed by the proposed invention is related to the test of such complex chips partitioned into blocks. It is desired to control test resources (e.g. test controllers or simple scan chains) using a method that will be compatible with new hierarchical design methodologies. The IEEE 1149.1 Test Access Port (TAP) is a popular way for controlling test resources on a chip. However, it is no longer practical to have this single test access circuit (TAC) in direct control of all test resources because of the number of connections between the TAP and the test resources that causes layout congestion around the TAP and because it would suggest a non-standard test interface for each block that would depend on the number and type of test resources in it. The latter issue is clearly not acceptable especially for blocks obtained from third parties. It is also an issue when the blocks are designed concurrently and the test resources are actually not known until the last minute.
In an effort to obviate these problems, and emerging IEEE P1500 standard proposes a test access circuit to de-centralize the control of test resources. The proposed test access circuit is similar to the IEEE 1149.1 Test Access Port (TAP) in that it has an instruction register and control circuitry that provides access to the various test resources. More specifically, it has an external interface consisting of at least a serial input, a serial output, a clock and a number of control inputs for use in configuring the test access circuit to perform an access to its instruction register or one of the test resources under its control. It also has an internal interface consisting of at least a serial output, a number of serial inputs corresponding to the number of test resources under its control and a number of control outputs for the same test resources.
The ultimate goal is to perform operations on test resources connected to a test access circuit connected at an arbitrary level of test access circuit hierarchy. As mentioned above, test resources can consist of test controllers or simple scan chains. There are two types of operations to be performed on test controllers. The first type consists of all operations related to the execution of a test whereas the second type consists of all operations related to the preparation of a test or diagnosis. The first type only requires access to the instruction register of the test access circuit connected to the test controller of interest. The second type also requires access to test data registers that are internal to the test controller.
Methods have been proposed to interconnect test access circuits. Muradali et al U.S. Pat. No. 6,191,603 granted on Feb. 20, 2001 for xe2x80x9cModular Embedded Test System for Use in Integrated Circuitsxe2x80x9d, suggests concatenating the serial input and output of all test access circuits of an integrated circuit. There is no mechanism for individually enabling only one test access circuit. Although simple, this approach requires loading instructions in all test access circuits every time an instruction change is needed in any one of the test access circuits. This results in longer times to load instructions. Also, the method is not compatible with a block based design approach because it is not possible to verify blocks independently of other blocks and without any knowledge of the contents of other blocks which might not be defined. Other disadvantages of this method is that a failure in a single test access circuit can prevent the user from running any internal or external test and make it very difficult to diagnose the source of the problem.
Dervisoglu et al WO 01/53844 published on Jul. 26, 2001 for xe2x80x9cHierarchical Test Circuit Structure for Chips with Multiple Circuit Blocksxe2x80x9d uses a different method that partially addresses the problem of long instruction streams. Dervisoglu introduces the concept of test access circuit hierarchy where test operations are transferred downward and upward in the hierarchy. A child TAC is selected by setting a bit in the instruction register of the parent TAC that is reset/deselected once a bit in the instruction register of the child TAC is set. The bit in the instruction register of the parent TAC is then cleared which, in turn, causes the child to be reset/deselected. Child TACs are reset as soon as they are deselected. This limitation does not allow running test controllers in parallel in different TACs. The architecture still requires concatenating TAC circuits at a same level of hierarchy, requiring sending long, instruction streams (although shorter than those of Muradali) to groups of TACs at the same time. The protocol also makes it difficult to navigate quickly through the test access circuit hierarchy especially when test resources, like test/BIST controllers, need to be accessed concurrently in different branches of the hierarchy. A malfunction of the child TAC circuits can be fatal for the parent TAC and reduce the possibility of diagnosing problems.
One of the primary functions of the TACs discussed in both Muradali and Dervisoglu is to configure a block in an external test mode to verify the connections and logic between blocks. TACs at a given level of test hierarchy need to receive a specific instruction from the parent block to be configured in that mode. In addition, there is no standard for this instruction (as opposed to the IEEE 1149.1 standard). Both of these factors complicate entering the external test mode. Also, there is no provision for including the logic of child TACs as part of the external test mode to facilitate the identification and diagnosis of faulty child TACs.
The test access circuit hierarchy consists of a test access circuit at the first (or top) level of a block and a certain number of test access circuits and test resources (e.g. scan chain, test controllers) connected to it as shown in FIG. 2. These test access circuits and test controllers constitute a second level of the test access circuit hierarchy. Each test access circuit of the second level can, in turn, control any number of test access circuits and test controllers which constitute a third level of the test access circuit hierarchy and so on. The last level of this hierarchy consists only of test controllers. When the block is the entire chip, the test access circuit at the first level of hierarchy is preferably an IEEE 1149.1 TAP. The test access circuit hierarchy does not necessarily depend on the actual design hierarchy.
One aspect of the present invention is generally defined as an improvement in a test access circuit for use in accessing test controllers in an integrated circuit having a hierarchy of test access circuits which control respective test resources in the integrated circuit, the improvement comprising a test access circuit instruction register having a child test access circuit configuring register which is configurable for serial interconnection with other registers of the instruction register when the test access circuit is configured in instruction register access mode and which serially connected in a scan path between a serial input and a serial output when the test access circuit is configured in a data register access mode. As will be seen, the configuring register simplifies and facilitates configuring parent test access circuits of circuits being accessed.
Another aspect of the present invention is generally defined as a method of accessing a test controller in an integrated circuit having a plurality of test access circuits arranged in a plurality of levels of test access circuit (TAC) hierarchy including a top-level TAC and at least one child TAC connected to the test controller, the method comprising loading an instruction into the top-level TAC to select a test port corresponding to a child TAC; and configure the child TAC to perform an instruction register access by setting a child instruction register select bit to an active value; and loading an instruction into the child TAC to select a test port corresponding to the test controller; and configure the test controller to perform desired test operations by setting test controller control bits to values corresponding to the desired operations.
A recursive embodiment of the method is generally defined as a method of configuring test access circuits for accessing test controllers in an integrated circuit having a hierarchy of test access circuits which control test resources in the integrated circuit, the method comprising, for each test access circuit in a scan path between a serial input and a serial output and containing a serial input and serial output of a grandparent test access circuit of a target test controller, loading an instruction into the test access circuit to insert the instruction register of a selected child test access circuit into the scan path; and replacing the instruction register of the test access circuit in the scan path by a child test access circuit configuring register of the instruction register of the test access circuit.